1. Field of the Invention
The present invention relates generally to a method of fabricating a capacitor landing pad. More particularly, the present invention relates to a method for fabricating a landing pad of a storage node in a dynamic random access memory (DRAM) device and the formed structure thereof.
2. Description of the Prior Art
As electronic products develop toward the direction of miniaturization, the design of dynamic random access memory (DRAM) units also moves toward the direction of higher integration and higher density. Since the nature of a DRAM unit with buried gate structures has the advantage of possessing longer carrier channel length within a semiconductor substrate thereby reducing capacitor leakage, it has been gradually used to replace conventional DRAM unit with planar gate structures.
Typically, a DRAM unit with buried gate structure includes a transistor device and a charge storage element to receive electrical signals from bit lines and word lines. With the rapid increase in the degree of integration on the DRAM, the size of the capacitor landing pad is also smaller. However, due to the bottleneck of the process technology, an unaligned situation at an exposure step used to define the location of the capacitor landing pad often occurs. The error margin is very small, resulting in the subsequent short circuit between the capacitor landing pads and the bit lines when the capacitor landing pads are formed. Therefore, there still exists many defects in the manufacturing process of the DRAM cell with the buried gate structure, and the efficiency and reliability of the related memory device need to be further improved.